Efficient Checksum Calculation using Reduction Trees

As network traffic throughput requirements continue to increase dramatically, network processors are adding specialized instructions that accelerate the more common arithmetic operations. An example is the checksum, which appears in several popular protocols to guard against using corrupted packets. This paper presents two approaches to checksum calculation that provide significant performance improvement over conventional methods. These approaches use reduction trees similar to those found in parallel multipliers to produce two operands for final summation. Reduction trees are appropriate when an array of words is available to be summed at one time, in contrast to serial summing of word pairs. The two methods vary in the design of the reduction tree. The first approach, leveled reduction based checksumming, uses predefined array sizes of partial sums, leading to a single circuit design. This approach has the benefit of fixed, design-once circuit parameters. The second approach, 3-to-2 reduction based checksumming, takes a greedy approach to reducing as many application words as possible at each stage. This approach has the benefit of parameterized circuit design amenable to automatic generation of reduction stages to fit application array size. Both approaches are suitable for a variety of circuit implementations.